1. Field of the Invention
This invention relates generally to soft switching switch mode power converters, and more particularly, to soft switching buck, buck-boost and boost switch mode power converters suitable for high power and high voltage applications such as plasma processing.
2. Brief Description of the Prior Art
It is generally desirable to operate switching power supplies at the highest frequency that is practical for a particular circuit. Operating at higher frequencies allows the inductor and capacitor values in a power supply to be reduced, and this reduces physical size and cost, and also enables improvements in the transient response of the power supply. Reducing the energy available for delivery to plasma arcs is also a desirable goal. High-frequency operation allows the use of smaller output filter capacitors, which store less energy than larger capacitors, and this reduces the energy that can be supplied to plasma arcs.
The operating frequencies prior art power supplies that utilize hard-switching power converters are limited because the switching losses can become prohibitively high as the operating frequency is increased.
FIG. 1 shows a prior art hard-switched power converter cell HSPCC that can be used to implement prior art hard-switched buck, buck-boost and boost power converters as shown in FIGS. 4–6 respectively. The hard-switched power converter cell HSPCC has three terminals: an active terminal AT, a passive terminal PT, and an inductive terminal IT. The power converter cell is comprised of a switch assembly SA and an inductor L. The switch assembly has an active switch terminal AST that is connected to the active terminal AT, a passive switch terminal PST that is connected to the passive terminal PT and a common switch terminal CST. The inductor L is connected between the common switch terminal CST and the converter inductive terminal IT.
The switch assembly has two switches: switch SAC that is connected between active switch terminal AST and common switch terminal CST, and switch SPC that is connected between passive switch terminal PST and common switch terminal CST. Switch SAC always comprises an active switch such as a transistor, and may also comprise an anti-parallel diode, while the SPC switch may comprise a diode, an active switch or both.
FIGS. 2 and 3 show two implementations of switch assembly SA in which switch SAC comprises an active switch SA connected in parallel with an anti-parallel diode APD, and in which switch SPC is a freewheeling diode FD. Ideally, the two switches in a switch assembly SA are never on simultaneously, but in hard-switched power that operate in a manner such that the currents in the filter inductors do not reach zero within a switching cycle (continuous conduction mode), a freewheeling diode must be turned off every time a switching transistor is turned on. A reverse current called the reverse-recovery current flows through the freewheeling diodes during the time interval when they are being turned off. The time it takes for a diode to turn off is called the reverse-recovery time. During the reverse-recovery time interval, a large diode reverse-recovery current to flows through the switches while the voltage across them is high. This produces switching losses that may be prohibitively high in hard switching power converters that operate at high voltage and power levels while switching at high frequencies.
Switch assemblies having SPC switches that are implemented as freewheeling diodes may be categorized as positive switch assemblies such as the PSA of FIG. 2, or negative switch assemblies such as the NSA of FIG. 3. A positive switch assembly blocks current from flowing between the active switch terminal AST and common switch terminal CST while the SAC switch is off and the active switch terminal AST is positive with respect to the common switch terminal CST. A negative switch assembly blocks current from flowing between the common and active switch terminals while the SAC switch is off and the active switch terminal is negative with respect to the common switch terminal.
FIGS. 4–6 show hard-switched power converters that are implemented with hard-switched power converter cells. FIG. 4 shows a hard-switched buck power converter HSBKPC, FIG. 5 shows a hard-switched buck-boost power converter HSBPC, and FIG. 6 shows a hard-switched boost power converter HSBTPC. Each of the power converters in FIGS. 4–6 has a converter input terminal CIT, a converter common terminal CCT, and a converter output terminal COT. Input power is supplied between the input and common terminals having an input voltage Vin, and power is delivered between the output and common terminals, between which there is an output voltage Vout. The interconnection arrangement among the power converter cell terminals and the power converter terminals determines whether the power converter is a hard-switched buck power converter HSBKPC, a hard switched buck-boost power converter HSBBPC or a hard switched boost power converter HSBTPC. Each power converter shown in FIGS. 4–6 has a converter input capacitor CIC connected between the input terminal and the common terminal, and a converter output capacitor COC connected between the output terminal and the common terminal.
Hard-switching power converter cells HSPCC can be implemented with either a set of positive switch assemblies or a set of negative switch assemblies. A positive hard-switched power converter cell is defined as a power converter cell that is implemented with one or more positive switch assemblies. Similarly, a negative hard-switched power converter cell is defined as a power converter cell that is implemented with one or more negative switch assemblies. The choice of whether to use positive or negative power converter cells depends on the polarity of the voltage to be converted and the converter topology. Positive hard-switched power converter cells PHSPCC are used to implement hard-switched buck HSBKPC and hard-switched buck-boost HSBBPC power converters when the input voltage Vin is positive (the converter input terminal CIT is positive with respect to the converter common terminal CCT), and also with hard-switched boost power converters HSBTPC that have negative input voltages (the converter input terminal CIT is negative with respect to the converter common terminal CCT). Conversely, negative hard-switched power converter cells NHSPCC are used in hard-switched buck HSBKPC and hard-switched buck-boost HSBBPC power converters that have negative input voltages, and also in hard-switched boost power converters HSBTPC that have positive input voltages.
The dashed lines in FIG. 4 indicate that multiple power converter cells may be connected in parallel order to share input and output currents of the power converter among two or more converter cells. Parallel-connected power converter cells are preferably operated with an interleaved switching pattern to reduce ripple in the input and output currents. If N converters are connected in parallel, then the switches are preferably operated with an interleaving phase angle difference of 360°/N. Although it is not shown in FIGS. 5 and 6, these power converters may also be implemented with parallel-connected power converter cells.
Interleaved hard-switched power converters are generally known in the prior art. They are commonly used for microprocessor VRM applications with very high output currents and very low output voltages. Having a low output voltage allows use of very fast low voltage diodes, so the switching losses are negligible. In general, high voltage diodes turn off more slowly than low voltage diodes, so switching losses are a particular problem for high-frequency power converters that operate at high voltages and high power levels. When hard-switched power converters are used in high-voltage and high-power applications as disclosed in U.S. Pat. No. 6,211,657, the switching losses will be considerable when the power converter is operated at high switching frequencies.
FIG. 7 shows a prior art interleaved hard-switched buck power converter HSBKPC that is based on FIGS. 2 and 4. The power converter has two parallel-connected positive hard switching power converter cells, PHSPCC1 and PHSPCC2, and it is like the interleaved converter disclosed in U.S. Pat. No. 6,211,657. FIG. 8 shows typical waveforms for an interleaved hard-switched power converter such as the one in FIG. 7 in which slower high voltage diodes are used. The current waveform plots of FIG. 8 have vertical scales of 10 A per division.
The waveforms in FIG. 8 were obtained from a computer simulation of the buck power converter BKPC of FIG. 7 with the following characteristics: input voltage Vin=750 VDC, output voltage Vout=400 VDC, output current Iout=62.5 A, switching period Ts=64 μs, 600 μH inductors L1 and L2, and a 10 μF converter output capacitor COC. The capacitance of COC used in the simulation was selected so that the output ripple voltage was negligible, but much smaller capacitors can be used with converters that are intended to operate loads where high-frequency ripple is not critical, such as typical dc plasma loads. The power converter was supplied by an ideal voltage source in the simulation, so the converter input capacitor was not required.
As can be seen in FIG. 8, diode FD1 is conducting when switch SW1 turns on at time t0. A large reverse-recovery current IRD1 flows through FD1 as it is being turned off by SW1. The same thing happens with SW2 and FD2 at time Ts/2. The freewheeling diode waveforms IFD1 and IFD2 illustrate how the peak reverse-recovery currents IRD1 and IRD2 of diodes FD1 and FD2 may be greater than their peak forward operating currents. The large reverse-recovery currents of the freewheeling diodes cause high power dissipation in switches SW1 and SW2 because the voltage across the switches is high during the turn-on switching transition interval. The diode reverse-recovery currents also cause considerable power dissipation in the diodes. Just before a diode is fully turned off, the voltage across it rises while current is still flowing, and this produces high turn-off power losses in the diode due to the simultaneous presence of high voltage and high current.
Because the same switching cells are used in hard-switched interleaved buck-boost and boost power converters, these converters have switching waveforms that are similar to the ones illustrated in FIG. 8. Large current spikes in the freewheeling diodes also occur in hard-switched non-interleaved power converters.
The turn-on losses in switches due to diode reverse-recovery currents can be reduced by adding circuitry that results in having zero, or relatively low, currents flowing through the switches as they are turned on. The turnoff losses of the diodes can be greatly decreased by reducing the current through them gradually instead of suddenly during the commutation interval.
One prior art approach to reducing switching losses due to diode reverse-recovery currents is to use auxiliary or pilot switches and inductors as taught in U.S. Pat. No. 5,307,004. There are two significant drawbacks to this approach. Although the pilot switches and diodes do not process much power in comparison to the main switches and diodes, their sizes are not proportionally smaller in high voltage power converters due to insulation requirements. The cost and size of the driver circuits for the pilot switches are also not proportionally smaller.
U.S. Pat. No. 6,184,666 discloses a buck converter with parallel-connected switches that process equal amounts of power and have equal power dissipation, but the converter does not have soft switching. U.S. Pat. No. 5,204,809 discloses hard-switched synchronous interleaved buck converters with coupled inductors. It teaches that the coupling coefficient should be less than about 0.9, with the optimal value being around 0.5. U.S. Pat. No. 6,426,883 discloses a power converter that uses equal-sized parallel-connected switching components and commutation inductors to achieve soft switching, but the switching pattern allows only one of the paralleled switches to have soft switching while the other switch has hard switching. In order to balance the switching losses, the switching pattern is periodically reversed so that each switch has soft switching half of the time.
For higher-voltage applications, hard-switched power converter cells can be connected in a stacked arrangement to implement hard-switched stacked buck HSSBKPC power converters, hard-switched stacked buck-boost HSSBEPC power converters and hard-switched stacked boost HSSBTPC power converters as shown in FIGS. 9, 10 and 11 respectively. Each of these converters has one positive hard-switched power converter cell, PHSPCC, and one negative hard-switched power converter cell, NHSPCC. Stacking two power converter cells in the configurations illustrated in FIGS. 9–11 allows the operating voltages to be twice those obtainable with non-stacked power converters when using equivalent power converter cells.
U.S. Pat. No. 5,932,995 shows that stacked buck converters can be implemented with hard-switched power converter cells. Various hard-switched stacked power converters are described in: Xinbo Ruan et al., “Three-level converters—a new approach for high voltage and high power DC-to-DC conversion,” IEEE 2002 Power Electronics Specialists Conference, vol. 2, pp. 663–668. These hard-switched power converters will have high switching losses when operated at high frequencies in high voltage and high power applications.
It would be desirable if there were provided a soft switching power converter suitable for high power and high voltage applications in which the switches have low turn-on losses, and the diodes have low turn-off losses. It would furthermore be desirable if there were provided a soft switching power converter suitable for high power and high voltage applications in which the diodes and switches in parallel-connected switching assemblies process the same level of power, and are operated with a switching pattern that allows soft switching for each parallel-connected switching assembly.